The present invention relates to a method of forming a wiring in a multi-layer wiring substrate, and particularly to an improvement in a method of forming an opening portion for inter-layer connection. Further, the present invention relates to a method of arranging devices and a method of manufacturing an image display system by using the method of forming a wiring.
In the case of arranging light-emitting devices in a matrix form to assemble an image display system, it has been a practice to form the devices directly on a substrate as in the cases of a liquid crystal display system (LCD) and a plasma display panel (PDP), or to arrange singular LED packages as in the case of a light-emitting diode display (LED display). For example, in the case of an image display system such as the LCD and the PDP, the devices cannot be separated, so that it has been a practice to form the devices at intervals equal to the pixel pitch of the image display system from the beginning of the manufacture process.
On the other hand, in the case of the LED display, it has been a practice to take out the LED chips after dicing, and connect the LED chips individually to external electrodes by wire bonding or bump connection by flip chips, thereby packaging. In this case, the LED chips are arranged at the pixel pitch of the image display system before or after the packaging, and the pixel pitch is independent from the pitch of the devices at the time of forming the devices.
Since the LED (light-emitting diode) being a light-emitting device is expensive, the cost of the image display system using LEDs can be lowered by producing a multiplicity of LED chips from a single sheet of wafer. Namely, when the size of the LED chips having hitherto been about 300 μm square is made to be several tens of μm square and the LED chips are connected to manufacture an image display system, the price of the image display system can be lowered.
In view of the above, a technology has developed in which devices are produced in a high degree of integration, and the devices are moved into a wider area while being spaced wider apart by transfer or the like to constitute a comparatively large sized display system such as an image display system. For example, there have been known such technologies as a thin film transfer method described in U.S. Pat. No. 5,438,241 and a method of producing a display transistor array panel described in Japanese Patent Laid-open No. Hei 11-142878. In the U.S. Pat. No. 5,438,241, a transfer method by which devices formed densely on a substrate are rearranged coarsely is disclosed. In this method, the devices are transferred onto an adhesive-coated extensible and contractable substrate, and thereafter the extensible and contractable substrate is extended in X direction and Y direction while monitoring the intervals and positions of the devices. Then, the devices on the extended substrate are transferred onto a required display panel. In the technology described in the Japanese Patent Laid-open No. Hei 11-142878, thin film transistors constituting a liquid crystal display portion on a first substrate are wholly transferred onto a second substrate, and then the thin film transistors are selectively transferred from the second substrate onto a third substrate corresponding to the pixel pitch.
In the cases of manufacturing the image display system by the transfer technologies as mentioned above, it is preferable to process the devices into chip component parts, in order to realize efficient transfer and highly accurate transfer. In order to process the devices into chip component parts, it suffices to bury the devices in an insulating material (for example, resin) and to dice the resultant body on a device basis.
When the devices are processed into the chip component parts, it is necessary to form opening portions (the so-called via holes) for making electrical connection in the insulating material in correspondence with electrodes of the devices. It is also necessary to form via holes for contriving inter-layer connection between a wiring layer provided on the substrate and the electrodes of the devices, after the final transfer. The formation of via holes is necessarily required not only in the transfer technologies but also in the cases of other multi-layer wiring substrates needing inter-layer connection, and knowing how to form the via holes is a major key to securing of reliability of the multi-layer wiring substrates. Conventionally, as a technique of forming via holes in a multi-layer wiring substrate, mechanical processing has been conducted. In mechanical processing, the so-called burrs are liable to be generated, and, therefore, mechanical processing is unsuited to fine processing. In addition, mechanical processing leads to generation of strains and may result in needless stresses being exerted on the substrate. Besides, as a method of forming minute via holes, such techniques as etching may also be contemplated, but these techniques require very intricate steps and are disadvantageous on a productivity basis. Particularly where a multi-layer body is composed of different materials, a plurality of times of etching by changing the etchant are required, leading to an increase in the number of processes and an increase in production cost. Further, in the formation of the via holes, the shape of the via holes is also an important factor. For example, where the via hole is so shaped that the side wall thereof is erected nearly vertically, upon formation of a wiring layer consisting of a metallic material, the metal would not easily be adhered onto the side wall, which leads to defects or failure in conduction.